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| author |   Paolo Bonzini <pbonzini@redhat.com> | 2024-05-10 10:49:02 -0400 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2024-05-10 13:20:18 -0400 |
| commit | 4232da23d75d173195c6766729e51947b64f83cd (patch) | |
| tree | 7eb1420b118d452c0b497bf6267ecdfb0a6d5931 /arch/x86/kvm/pmu.c | |
| parent | Merge branch 'kvm-sev-es-ghcbv2' into HEAD (diff) | |
| parent | LoongArch: KVM: Add mmio trace events support (diff) | |
| download | wireguard-linux-4232da23d75d173195c6766729e51947b64f83cd.tar.xz wireguard-linux-4232da23d75d173195c6766729e51947b64f83cd.zip | |
Merge tag 'loongarch-kvm-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson into HEAD
LoongArch KVM changes for v6.10
1. Add ParaVirt IPI support.
2. Add software breakpoint support.
3. Add mmio trace events support.
Diffstat (limited to '')
| -rw-r--r-- | arch/x86/kvm/pmu.c | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index c397b28e3d1b..a593b03c9aed 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -775,8 +775,20 @@ void kvm_pmu_refresh(struct kvm_vcpu *vcpu) pmu->pebs_data_cfg_mask = ~0ull; bitmap_zero(pmu->all_valid_pmc_idx, X86_PMC_IDX_MAX); - if (vcpu->kvm->arch.enable_pmu) - static_call(kvm_x86_pmu_refresh)(vcpu); + if (!vcpu->kvm->arch.enable_pmu) + return; + + static_call(kvm_x86_pmu_refresh)(vcpu); + + /* + * At RESET, both Intel and AMD CPUs set all enable bits for general + * purpose counters in IA32_PERF_GLOBAL_CTRL (so that software that + * was written for v1 PMUs don't unknowingly leave GP counters disabled + * in the global controls). Emulate that behavior when refreshing the + * PMU so that userspace doesn't need to manually set PERF_GLOBAL_CTRL. + */ + if (kvm_pmu_has_perf_global_ctrl(pmu) && pmu->nr_arch_gp_counters) + pmu->global_ctrl = GENMASK_ULL(pmu->nr_arch_gp_counters - 1, 0); } void kvm_pmu_init(struct kvm_vcpu *vcpu) |