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| author |   Peter Zijlstra <peterz@infradead.org> | 2021-04-14 14:45:43 +0200 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2021-06-03 08:59:11 +0200 |
| commit | a103713429035da799fa05c7da113f969c0df992 (patch) | |
| tree | 85a89c24739622476bcf2dc1198666a821487162 /arch | |
| parent | scsi: BusLogic: Fix 64-bit system enumeration error for Buslogic (diff) | |
| download | wireguard-linux-a103713429035da799fa05c7da113f969c0df992.tar.xz wireguard-linux-a103713429035da799fa05c7da113f969c0df992.zip | |
openrisc: Define memory barrier mb
[ Upstream commit 8b549c18ae81dbc36fb11e4aa08b8378c599ca95 ]
This came up in the discussion of the requirements of qspinlock on an
architecture. OpenRISC uses qspinlock, but it was noticed that the
memmory barrier was not defined.
Peter defined it in the mail thread writing:
As near as I can tell this should do. The arch spec only lists
this one instruction and the text makes it sound like a completion
barrier.
This is correct so applying this patch.
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
[shorne@gmail.com:Turned the mail into a patch]
Signed-off-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/openrisc/include/asm/barrier.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/openrisc/include/asm/barrier.h b/arch/openrisc/include/asm/barrier.h new file mode 100644 index 000000000000..7538294721be --- /dev/null +++ b/arch/openrisc/include/asm/barrier.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_BARRIER_H +#define __ASM_BARRIER_H + +#define mb() asm volatile ("l.msync" ::: "memory") + +#include <asm-generic/barrier.h> + +#endif /* __ASM_BARRIER_H */ |