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authorArd Biesheuvel <ard.biesheuvel@linaro.org>2018-08-23 17:48:45 +0100
committerHerbert Xu <herbert@gondor.apana.org.au>2018-09-04 11:37:04 +0800
commited6ed11830a9ded520db31a6e2b69b6b0a1eb0e2 (patch)
treebdf6908d874286a1dbd80884fbb9bccad6990a4a /crypto/algapi.c
parentcrypto: arm/ghash-ce - implement support for 4-way aggregation (diff)
downloadwireguard-linux-ed6ed11830a9ded520db31a6e2b69b6b0a1eb0e2.tar.xz
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crypto: arm64/aes-modes - get rid of literal load of addend vector
Replace the literal load of the addend vector with a sequence that performs each add individually. This sequence is only 2 instructions longer than the original, and 2% faster on Cortex-A53. This is an improvement by itself, but also works around a Clang issue, whose integrated assembler does not implement the GNU ARM asm syntax completely, and does not support the =literal notation for FP registers (more info at https://bugs.llvm.org/show_bug.cgi?id=38642) Cc: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'crypto/algapi.c')
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