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| author |   Linus Walleij <linus.walleij@linaro.org> | 2023-01-10 20:43:07 +0100 |
|---|---|---|
| committer |   Herbert Xu <herbert@gondor.apana.org.au> | 2023-01-20 18:29:31 +0800 |
| commit | 319ad16d62d3da695faebd2d5def6be0d542f586 (patch) | |
| tree | cd6a3cee587ce926490769f1b29083f130e0172a /crypto/essiv.c | |
| parent | crypto: aspeed - Replace zero-length array with flexible-array member (diff) | |
| download | wireguard-linux-319ad16d62d3da695faebd2d5def6be0d542f586.tar.xz wireguard-linux-319ad16d62d3da695faebd2d5def6be0d542f586.zip | |
crypto: stm32 - Use accelerated readsl/writesl
When reading or writing crypto buffers the inner loops can
be replaced with readsl and writesl which will on ARM result
in a tight assembly loop, speeding up encryption/decryption
a little bit. This optimization was in the Ux500 driver so
let's carry it over to the STM32 driver.
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Lionel Debieve <lionel.debieve@foss.st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'crypto/essiv.c')
0 files changed, 0 insertions, 0 deletions