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| author |   Luca Ceresoli <luca@lucaceresoli.net> | 2020-07-23 09:41:12 +0200 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2020-07-23 15:33:43 -0700 |
| commit | 45c940184b501fc65592432a269b7a34cf2237b6 (patch) | |
| tree | 6d11b308df4656b08cf19139f0b9e1eb9ac0c4c6 /drivers/clk/clk-versaclock5.c | |
| parent | MAINTAINERS: take over IDT VersaClock 5 clock driver (diff) | |
| download | wireguard-linux-45c940184b501fc65592432a269b7a34cf2237b6.tar.xz wireguard-linux-45c940184b501fc65592432a269b7a34cf2237b6.zip | |
dt-bindings: clk: versaclock5: convert to yaml
Convert to yaml the VersaClock bindings document. The mapping between
clock specifier and physical pins cannot be described formally in yaml
schema, then keep it verbatim in the description field.
Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
Link: https://lore.kernel.org/r/20200723074112.3159-4-luca@lucaceresoli.net
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/clk-versaclock5.c')
0 files changed, 0 insertions, 0 deletions