diff options
| author |   Elaine Zhang <zhangqing@rock-chips.com> | 2021-03-15 16:56:07 +0800 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2021-03-21 11:10:58 +0100 |
| commit | a3561e77cf3ca0937227ba13744d84fc46e5eb4b (patch) | |
| tree | 14bb72f7a1a97dcf5fc532dff1d4beec99bb9bbb /drivers/clk/rockchip/clk-rk3328.c | |
| parent | dt-binding: clock: Document rockchip, rk3568-cru bindings (diff) | |
| download | wireguard-linux-a3561e77cf3ca0937227ba13744d84fc46e5eb4b.tar.xz wireguard-linux-a3561e77cf3ca0937227ba13744d84fc46e5eb4b.zip | |
clk: rockchip: support more core div setting
Use arrays to support more core independent div settings.
A55 supports each core to work at different frequencies, and each core
has an independent divider control.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20210315085608.16010-4-zhangqing@rock-chips.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk/rockchip/clk-rk3328.c')
| -rw-r--r-- | drivers/clk/rockchip/clk-rk3328.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c index 2429b7c2a8b3..267ab54937d3 100644 --- a/drivers/clk/rockchip/clk-rk3328.c +++ b/drivers/clk/rockchip/clk-rk3328.c @@ -130,9 +130,10 @@ static struct rockchip_cpuclk_rate_table rk3328_cpuclk_rates[] __initdata = { }; static const struct rockchip_cpuclk_reg_data rk3328_cpuclk_data = { - .core_reg = RK3328_CLKSEL_CON(0), - .div_core_shift = 0, - .div_core_mask = 0x1f, + .core_reg[0] = RK3328_CLKSEL_CON(0), + .div_core_shift[0] = 0, + .div_core_mask[0] = 0x1f, + .num_cores = 1, .mux_core_alt = 1, .mux_core_main = 3, .mux_core_shift = 6, |