diff options
| author |   Andrew Bresticker <abrestic@chromium.org> | 2013-09-25 14:12:48 -0700 |
|---|---|---|
| committer |   Tomasz Figa <t.figa@samsung.com> | 2014-01-08 18:02:41 +0100 |
| commit | 547f33509ccc6e016df02600d377778b75e26a7b (patch) | |
| tree | 2b534dc529d2b747c4fe50e48019aa0a4cd7a0f3 /drivers/clk/samsung/clk-exynos-audss.c | |
| parent | clk: exynos-audss: convert to platform device (diff) | |
| download | wireguard-linux-547f33509ccc6e016df02600d377778b75e26a7b.tar.xz wireguard-linux-547f33509ccc6e016df02600d377778b75e26a7b.zip | |
clk: exynos-audss: allow input clocks to be specified in device tree
This allows the input clocks to the Exynos AudioSS block to be
specified via device-tree bindings. Default names will be used
when an input clock is not given.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Diffstat (limited to 'drivers/clk/samsung/clk-exynos-audss.c')
| -rw-r--r-- | drivers/clk/samsung/clk-exynos-audss.c | 25 |
1 files changed, 20 insertions, 5 deletions
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index 1d8f6770ccfe..19a0d874931e 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -28,10 +28,6 @@ static struct clk_onecell_data clk_data; #define ASS_CLK_DIV 0x4 #define ASS_CLK_GATE 0x8 -/* list of all parent clock list */ -static const char *mout_audss_p[] = { "fin_pll", "fout_epll" }; -static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" }; - #ifdef CONFIG_PM_SLEEP static unsigned long reg_save[][2] = { {ASS_CLK_SRC, 0}, @@ -68,6 +64,10 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) { int i, ret = 0; struct resource *res; + const char *mout_audss_p[] = {"fin_pll", "fout_epll"}; + const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"}; + const char *sclk_pcm_p = "sclk_pcm0"; + struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); reg_base = devm_ioremap_resource(&pdev->dev, res); @@ -85,11 +85,23 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) clk_data.clks = clk_table; clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS; + pll_ref = devm_clk_get(&pdev->dev, "pll_ref"); + pll_in = devm_clk_get(&pdev->dev, "pll_in"); + if (!IS_ERR(pll_ref)) + mout_audss_p[0] = __clk_get_name(pll_ref); + if (!IS_ERR(pll_in)) + mout_audss_p[1] = __clk_get_name(pll_in); clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss", mout_audss_p, ARRAY_SIZE(mout_audss_p), CLK_SET_RATE_NO_REPARENT, reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); + cdclk = devm_clk_get(&pdev->dev, "cdclk"); + sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio"); + if (!IS_ERR(cdclk)) + mout_i2s_p[1] = __clk_get_name(cdclk); + if (!IS_ERR(sclk_audio)) + mout_i2s_p[2] = __clk_get_name(sclk_audio); clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s", mout_i2s_p, ARRAY_SIZE(mout_i2s_p), CLK_SET_RATE_NO_REPARENT, @@ -123,8 +135,11 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) "sclk_pcm", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 4, 0, &lock); + sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in"); + if (!IS_ERR(sclk_pcm_in)) + sclk_pcm_p = __clk_get_name(sclk_pcm_in); clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm", - "div_pcm0", CLK_SET_RATE_PARENT, + sclk_pcm_p, CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 5, 0, &lock); for (i = 0; i < clk_data.clk_num; i++) { |