diff options
| author |   Tejas Patel <tejas.patel@xilinx.com> | 2020-03-12 14:31:39 -0700 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2020-05-26 17:59:12 -0700 |
| commit | 2ce7e495dab4647055f6cf300bc66870dc8a7cab (patch) | |
| tree | c8eac2761db5a423805e72c5f5d07f483bd5ceec /drivers/clk/zynqmp | |
| parent | clk: zynqmp: Add support for custom type flags (diff) | |
| download | wireguard-linux-2ce7e495dab4647055f6cf300bc66870dc8a7cab.tar.xz wireguard-linux-2ce7e495dab4647055f6cf300bc66870dc8a7cab.zip | |
clk: zynqmp: Update fraction clock check from custom type flags
Older firmware version sets BIT(13) in clkflag to mark a
divider as fractional divider. Updated firmware version sets BIT(4)
in type flags to mark a divider as fractional divider since
BIT(13) is defined as CLK_DUTY_CYCLE_PARENT in the common clk
framework flags.
To support both old and new firmware version, consider BIT(13) from
clkflag and BIT(4) from type_flag to check if divider is fractional
or not.
To maintain compatibility BIT(13) of clkflag in firmware will not be
used in future for any purpose and will be marked as unused.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Link: https://lkml.kernel.org/r/1584048699-24186-3-git-send-email-jolly.shah@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/zynqmp')
| -rw-r--r-- | drivers/clk/zynqmp/divider.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index f7b35459ad0b..79a294488e84 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -25,7 +25,8 @@ #define to_zynqmp_clk_divider(_hw) \ container_of(_hw, struct zynqmp_clk_divider, hw) -#define CLK_FRAC BIT(13) /* has a fractional parent */ +#define CLK_FRAC BIT(13) /* has a fractional parent */ +#define CUSTOM_FLAG_CLK_FRAC BIT(0) /* has a fractional parent in custom type flag */ /** * struct zynqmp_clk_divider - adjustable divider clock @@ -320,7 +321,8 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name, init.num_parents = 1; /* struct clk_divider assignments */ - div->is_frac = !!(nodes->flag & CLK_FRAC); + div->is_frac = !!((nodes->flag & CLK_FRAC) | + (nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC)); div->flags = nodes->type_flag; div->hw.init = &init; div->clk_id = clk_id; |