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| author |   Andre Przywara <andre.przywara@arm.com> | 2020-01-02 01:26:56 +0000 |
|---|---|---|
| committer |   Maxime Ripard <maxime@cerno.tech> | 2020-01-03 10:39:27 +0100 |
| commit | 396c95e8b1385e3dac16d46227f570598b31f0f7 (patch) | |
| tree | e19159052df6bf0f1d8944462e4f27b77fe7d95b /drivers/clocksource/hyperv_timer.c | |
| parent | ARM: dts: sun8i: R40: Upgrade GICC reg size to 8K (diff) | |
| download | wireguard-linux-396c95e8b1385e3dac16d46227f570598b31f0f7.tar.xz wireguard-linux-396c95e8b1385e3dac16d46227f570598b31f0f7.zip | |
ARM: dts: sun8i: R40: Add PMU node
The ARM Cortex-A7 cores used in the Allwinner R40 SoC have their usual
Performance Monitoring Unit (PMU), which allows perf to use hardware
events.
The SoC integrator just needs to connect each per-core interrupt line
to the GIC. The R40 manual does not really mention those IRQ lines, but
experimentation in U-Boot shows that interrupts 152-155 are connected to
the four cores (similar to the A20).
Tested on a Bananapi M2 Berry, with perf and taskset to confirm the
association between cores and interrupts.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions