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| author |   Kishon Vijay Abraham I <kishon@ti.com> | 2019-12-16 15:27:06 +0530 |
|---|---|---|
| committer | Kishon Vijay Abraham I <kishon@ti.com> | 2020-01-08 12:58:06 +0530 |
| commit | b872936f5757412ec11039ffe895e1b9249d6b68 (patch) | |
| tree | c3fcb333539d6f4542d5db19e79f81a009dc0154 /drivers/clocksource/timer-stm32-lp.c | |
| parent | phy: cadence: Sierra: Configure both lane cdb and common cdb registers for external SSC (diff) | |
| download | wireguard-linux-b872936f5757412ec11039ffe895e1b9249d6b68.tar.xz wireguard-linux-b872936f5757412ec11039ffe895e1b9249d6b68.zip | |
phy: cadence: Sierra: Get reset control "array" for each link
A link may have multiple lanes each with a separate reset. Get
reset control "array" in order to reset all the lanes associated
with the link.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'drivers/clocksource/timer-stm32-lp.c')
0 files changed, 0 insertions, 0 deletions