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| author |   Meng Yu <yumeng18@huawei.com> | 2021-03-04 14:35:45 +0800 |
|---|---|---|
| committer |   Herbert Xu <herbert@gondor.apana.org.au> | 2021-03-13 00:04:02 +1100 |
| commit | 9b94ae729068f6608ec7364dea891ee86dd3dad2 (patch) | |
| tree | ae12501b0926b058c2a2b94006585e8e06d90f54 /drivers/crypto/hisilicon/hpre/hpre.h | |
| parent | crypto: hisilicon/hpre - add version adapt to new algorithms (diff) | |
| download | wireguard-linux-9b94ae729068f6608ec7364dea891ee86dd3dad2.tar.xz wireguard-linux-9b94ae729068f6608ec7364dea891ee86dd3dad2.zip | |
crypto: hisilicon/hpre - add algorithm type
Algorithm type is brought in to get hardware HPRE queue
to support different algorithms.
Signed-off-by: Meng Yu <yumeng18@huawei.com>
Reviewed-by: Zaibo Xu <xuzaibo@huawei.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto/hisilicon/hpre/hpre.h')
| -rw-r--r-- | drivers/crypto/hisilicon/hpre/hpre.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/crypto/hisilicon/hpre/hpre.h b/drivers/crypto/hisilicon/hpre/hpre.h index cc50f23947cf..02193e1ac694 100644 --- a/drivers/crypto/hisilicon/hpre/hpre.h +++ b/drivers/crypto/hisilicon/hpre/hpre.h @@ -10,6 +10,14 @@ #define HPRE_PF_DEF_Q_NUM 64 #define HPRE_PF_DEF_Q_BASE 0 +/* + * type used in qm sqc DW6. + * 0 - Algorithm which has been supported in V2, like RSA, DH and so on; + * 1 - ECC algorithm in V3. + */ +#define HPRE_V2_ALG_TYPE 0 +#define HPRE_V3_ECC_ALG_TYPE 1 + enum { HPRE_CLUSTER0, HPRE_CLUSTER1, @@ -92,7 +100,7 @@ struct hpre_sqe { __le32 rsvd1[_HPRE_SQE_ALIGN_EXT]; }; -struct hisi_qp *hpre_create_qp(void); +struct hisi_qp *hpre_create_qp(u8 type); int hpre_algs_register(struct hisi_qm *qm); void hpre_algs_unregister(struct hisi_qm *qm); |