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| author | 2024-04-02 08:17:13 -0400 | |
|---|---|---|
| committer | 2024-04-02 08:17:13 -0400 | |
| commit | 5add703f6acad1c63f8a532b6de56e50d548e904 (patch) | |
| tree | be39a82716119cd8b7cf7e2734baf8cd9a80ceb7 /drivers/cxl/core/core.h | |
| parent | drm/i915/psr: Do not write ALPM configuration for PSR1 or DP2.0 Panel Replay (diff) | |
| parent | Linux 6.9-rc2 (diff) | |
| download | wireguard-linux-5add703f6acad1c63f8a532b6de56e50d548e904.tar.xz wireguard-linux-5add703f6acad1c63f8a532b6de56e50d548e904.zip | |
Merge drm/drm-next into drm-intel-next
Catching up on 6.9-rc2
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/cxl/core/core.h')
| -rw-r--r-- | drivers/cxl/core/core.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 3b64fb1b9ed0..bc5a95665aa0 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -90,4 +90,8 @@ enum cxl_poison_trace_type { long cxl_pci_get_latency(struct pci_dev *pdev); +int cxl_update_hmat_access_coordinates(int nid, struct cxl_region *cxlr, + enum access_coordinate_class access); +bool cxl_need_node_perf_attrs_update(int nid); + #endif /* __CXL_CORE_H__ */ |
