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| author |   Ben Widawsky <ben.widawsky@intel.com> | 2022-01-23 16:29:53 -0800 |
|---|---|---|
| committer |   Dan Williams <dan.j.williams@intel.com> | 2022-02-08 22:57:29 -0800 |
| commit | 53fa1bff3426344d466d91e81f076eab677d0ece (patch) | |
| tree | e29317f8652ba42a4da2a3b98d90c11d6b65865c /drivers/cxl | |
| parent | cxl/core/port: Make passthrough decoder init implicit (diff) | |
| download | wireguard-linux-53fa1bff3426344d466d91e81f076eab677d0ece.tar.xz wireguard-linux-53fa1bff3426344d466d91e81f076eab677d0ece.zip | |
cxl/core: Track port depth
In preparation for proving CXL subsystem usage of the device_lock()
order track the depth of ports with the expectation that shallower port
locks can be held over deeper port locks.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/164298419321.3018233.4469731547378993606.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl')
| -rw-r--r-- | drivers/cxl/core/port.c | 2 | ||||
| -rw-r--r-- | drivers/cxl/cxl.h | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 73ff42a05473..f287d87da6d6 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -362,6 +362,8 @@ struct cxl_port *devm_cxl_add_port(struct device *host, struct device *uport, if (IS_ERR(port)) return port; + if (parent_port) + port->depth = parent_port->depth + 1; dev = &port->dev; if (parent_port) rc = dev_set_name(dev, "port%d", port->id); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 621a70e023c1..7ade555076bc 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -252,6 +252,7 @@ struct cxl_walk_context { * @dports: cxl_dport instances referenced by decoders * @decoder_ida: allocator for decoder ids * @component_reg_phys: component register capability base address (optional) + * @depth: How deep this port is relative to the root. depth 0 is the root. */ struct cxl_port { struct device dev; @@ -260,6 +261,7 @@ struct cxl_port { struct list_head dports; struct ida decoder_ida; resource_size_t component_reg_phys; + unsigned int depth; }; /** |