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| author |   Paul Burton <paul.burton@imgtec.com> | 2017-09-21 23:24:39 -0700 |
|---|---|---|
| committer |   Thomas Gleixner <tglx@linutronix.de> | 2017-09-25 21:23:43 +0200 |
| commit | a08588ea486a5590b50c36f437dc86350271b250 (patch) | |
| tree | 18db0b04b2255a4e2f40cd3769a028fc966b61b8 /drivers/fpga/fpga-bridge.c | |
| parent | genirq: Check __free_irq() return value for NULL (diff) | |
| download | wireguard-linux-a08588ea486a5590b50c36f437dc86350271b250.tar.xz wireguard-linux-a08588ea486a5590b50c36f437dc86350271b250.zip | |
irqchip/mips-gic: Fix shifts to extract register fields
The MIPS GIC driver is incorrectly using __fls to shift registers,
intending to shift to the least significant bit of a value based upon
its mask but instead shifting off all but the value's top bit. It should
actually be using __ffs to shift to the first, not last, bit of the
value.
Apparently the system I used when testing commit 3680746abd87
("irqchip: mips-gic: Convert remaining shared reg access to new
accessors") and commit b2b2e584ceab ("irqchip: mips-gic: Clean up mti,
reserved-cpu-vectors handling") managed to work correctly despite this
issue, but not all systems do...
Fixes: 3680746abd87 ("irqchip: mips-gic: Convert remaining shared reg access to new accessors")
Fixes: b2b2e584ceab ("irqchip: mips-gic: Clean up mti, reserved-cpu-vectors handling")
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Link: https://lkml.kernel.org/r/20170922062440.23701-2-paul.burton@imgtec.com
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions