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| author |   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2024-08-18 19:29:04 +0200 |
|---|---|---|
| committer |   Jakub Kicinski <kuba@kernel.org> | 2024-08-20 15:28:41 -0700 |
| commit | 70d16e13368c0526eb3e2a326ed002183a087c21 (patch) | |
| tree | 5e83f6f82cdc0d85dd486975d35f430bb3614378 /drivers/fpga/xilinx-selectmap.c | |
| parent | dt-bindings: net: mediatek,net: add top-level constraints (diff) | |
| download | wireguard-linux-70d16e13368c0526eb3e2a326ed002183a087c21.tar.xz wireguard-linux-70d16e13368c0526eb3e2a326ed002183a087c21.zip | |
dt-bindings: net: renesas,etheravb: add top-level constraints
Properties with variable number of items per each device are expected to
have widest constraints in top-level "properties:" block and further
customized (narrowed) in "if:then:". Add missing top-level constraints
for reg, clocks, clock-names, interrupts and interrupt-names.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20240818172905.121829-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'drivers/fpga/xilinx-selectmap.c')
0 files changed, 0 insertions, 0 deletions