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| author | 2021-01-13 22:51:43 +0000 | |
|---|---|---|
| committer | 2021-01-14 07:53:14 +0000 | |
| commit | ca85e21846041f4beba0fff5e4fb8473d5723134 (patch) | |
| tree | be1d1fa323761deb4f5a0ef5143583010c70d186 /drivers/fpga/xilinx-spi.c | |
| parent | drm/i915/gt: Replace open-coded intel_engine_stop_cs() (diff) | |
| download | wireguard-linux-ca85e21846041f4beba0fff5e4fb8473d5723134.tar.xz wireguard-linux-ca85e21846041f4beba0fff5e4fb8473d5723134.zip | |
drm/i915/gt: Rearrange vlv workarounds
Some rcs0 workarounds were being incorrectly applied to the GT, and so
we failed to restore the expected register settings after a reset.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210113225144.30810-1-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/fpga/xilinx-spi.c')
0 files changed, 0 insertions, 0 deletions
