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| author |   Evan Quan <evan.quan@amd.com> | 2018-04-10 12:32:16 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2018-05-15 13:43:04 -0500 |
| commit | b8a5559112714bb328330dbf2a4a1912e8c7a462 (patch) | |
| tree | 7eb434043df825267477d2824a8a6ab0768a5890 /drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | |
| parent | drm/amdgpu: add MP1 and THM hw ip base reg offset (diff) | |
| download | wireguard-linux-b8a5559112714bb328330dbf2a4a1912e8c7a462.tar.xz wireguard-linux-b8a5559112714bb328330dbf2a4a1912e8c7a462.zip | |
drm/amd/pp: use soc15 common macros instead of vega10 specific
pp_soc15.h is vega10 specific. Update powerplay code to use soc15 common
macros defined in soc15_common.h.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c')
0 files changed, 0 insertions, 0 deletions