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| author |   Alex Deucher <alexander.deucher@amd.com> | 2022-05-24 10:02:16 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-06-03 16:45:00 -0400 |
| commit | 9d6b2041761ff6d5a33941919c8b5a805ecbed6c (patch) | |
| tree | c707981259273a6855a73077e5f8d916600ccd5e /drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | |
| parent | drm/amd/display: Halve DTB Clock Value for DCN32 (diff) | |
| download | wireguard-linux-9d6b2041761ff6d5a33941919c8b5a805ecbed6c.tar.xz wireguard-linux-9d6b2041761ff6d5a33941919c8b5a805ecbed6c.zip | |
drm/amdgpu: convert sienna_cichlid_populate_umd_state_clk() to use IP version
Rather than asic type.
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_device.c')
0 files changed, 0 insertions, 0 deletions