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| author |   Cruise Hung <Cruise.Hung@amd.com> | 2022-09-08 22:04:09 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2022-09-19 15:14:55 -0400 |
| commit | c1143ca2d523dee0f6012638068abd202a50a42b (patch) | |
| tree | 2aebd86073c4547d5498cce64a86394bd27af2a4 /drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | |
| parent | drm/amd/display: Display distortion after hotplug 5K tiled display (diff) | |
| download | wireguard-linux-c1143ca2d523dee0f6012638068abd202a50a42b.tar.xz wireguard-linux-c1143ca2d523dee0f6012638068abd202a50a42b.zip | |
drm/amd/display: Fix DP MST timeslot issue when fallback happened
[Why]
When USB4 DP link training failed and fell back to lower link rate,
the time slot calculation uses the verified_link_cap.
And the verified_link_cap was not updated to the new one.
It caused the wrong VC payload time-slot was allocated.
[How]
Updated verified_link_cap with the new one from cur_link_settings
after the LT completes successfully.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Cruise Hung <Cruise.Hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_job.c')
0 files changed, 0 insertions, 0 deletions