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| author |   James Zhu <James.Zhu@amd.com> | 2019-04-05 15:31:47 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-05-24 12:20:50 -0500 |
| commit | 5326ad54c5ef01a828cf5a942f6fdbf204ef7d3f (patch) | |
| tree | 95b5e837d320db447710126e301c96638a813c52 /drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | |
| parent | drm/amdgpu: add EDC counter register (diff) | |
| download | wireguard-linux-5326ad54c5ef01a828cf5a942f6fdbf204ef7d3f.tar.xz wireguard-linux-5326ad54c5ef01a828cf5a942f6fdbf204ef7d3f.zip | |
drm/amdgpu: add gfx9 gpr EDC workaround when RAS is enabled
When RAS is enabled, initializes the VGPRs/LDS/SGPRs and
resets EDC error counts. This is done in late_init, before
RAS TA GFX enable.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c')
0 files changed, 0 insertions, 0 deletions