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| author |   Haohui Mai <ricetons@gmail.com> | 2022-05-16 23:06:35 -0700 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2022-05-26 14:56:31 -0400 |
| commit | 842035543c0bfa35b1471e74094a107673815b01 (patch) | |
| tree | a69042584719def282b1234a98c5b5ee25fa164e /drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | |
| parent | drm/amdgpu: cleanup ctx implementation (diff) | |
| download | wireguard-linux-842035543c0bfa35b1471e74094a107673815b01.tar.xz wireguard-linux-842035543c0bfa35b1471e74094a107673815b01.zip | |
drm/amdgpu: Set CP_HQD_PQ_CONTROL.RPTR_BLOCK_SIZE correctly
Remove the accidental shifts on the values of RPTR_BLOCK_SIZE
in gfx_v8-v11. The bug essentially always programs the
corresponding fields to zero instead of the correct value.
The hardware clamps the min value to 5 so this resulted in a
value of 5 being programmed.
Signed-off-by: Haohui Mai <ricetons@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c')
0 files changed, 0 insertions, 0 deletions