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| author |   Ilya Bakoulin <ilya.bakoulin@amd.com> | 2024-01-03 09:42:04 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2024-01-15 18:35:38 -0500 |
| commit | b4e05bb1dec53fe28c3c88425aded824498666e5 (patch) | |
| tree | 31982e9818713b728c7fc4728e5639c0d60fb4d4 /drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | |
| parent | drm/amd/display: Floor to mhz when requesting dpp disp clock changes to SMU (diff) | |
| download | wireguard-linux-b4e05bb1dec53fe28c3c88425aded824498666e5.tar.xz wireguard-linux-b4e05bb1dec53fe28c3c88425aded824498666e5.zip | |
drm/amd/display: Clear OPTC mem select on disable
[Why]
Not clearing the memory select bits prior to OPTC disable can cause DSC
corruption issues when attempting to reuse a memory instance for another
OPTC that enables ODM.
[How]
Clear the memory select bits prior to disabling an OPTC.
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Ilya Bakoulin <ilya.bakoulin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c')
0 files changed, 0 insertions, 0 deletions