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| author |   Jinzhou Su <Jinzhou.Su@amd.com> | 2021-01-19 17:33:36 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2021-01-21 09:53:33 -0500 |
| commit | 860cc26a0179894648f031a6eab6945cb09bd796 (patch) | |
| tree | 2cd58dc8b029dd97cb9653f29f161e42908b0ee2 /drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | |
| parent | drm/amdgpu/pm: no need GPU status set since mmnbif_gpu_BIF_DOORBELL_FENCE_CNTL added in FSDL (diff) | |
| download | wireguard-linux-860cc26a0179894648f031a6eab6945cb09bd796.tar.xz wireguard-linux-860cc26a0179894648f031a6eab6945cb09bd796.zip | |
drm/amdgpu: Add RLC_PG_DELAY_3 for Vangogh
Driver should enable the CGPG feature for RLC in safe mode to
prevent any misalignment or conflict in middle of any power
feature entry/exit sequence.
Achieved by setting RLC_PG_CNTL.GFX_POWER_GATING_ENABLE = 0x1,
and RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG
hysteresis value in refclk count.
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c')
0 files changed, 0 insertions, 0 deletions