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| author |   Likun Gao <Likun.Gao@amd.com> | 2020-05-01 16:24:33 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-10-23 15:33:48 -0400 |
| commit | 4005809bb1f31fd3c23b42c24c90b15ed72746c0 (patch) | |
| tree | 17c795c14186163b682823e16cb00eb4cb332e0d /drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | |
| parent | drm/amdgpu: add GC 10.3 NOALLOC registers (diff) | |
| download | wireguard-linux-4005809bb1f31fd3c23b42c24c90b15ed72746c0.tar.xz wireguard-linux-4005809bb1f31fd3c23b42c24c90b15ed72746c0.zip | |
drm/amdgpu: add support to configure MALL for sienna_cichlid (v2)
Enable Memory Access at Last Level (MALL) feature for sienna_cichlid.
v2: drop module option. We need to add UAPI so userspace can
request MALL per buffer.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c')
0 files changed, 0 insertions, 0 deletions