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| author |   Felix Kuehling <Felix.Kuehling@amd.com> | 2019-08-29 21:18:43 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-09-13 17:36:08 -0500 |
| commit | 17da41bf00c849d809cb3cc5eebc43a1924736fd (patch) | |
| tree | 61b7419114c617b915c078a358e04fb8342f442c /drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | |
| parent | drm/amdgpu: Use optimal mtypes and PTE bits for Arcturus (diff) | |
| download | wireguard-linux-17da41bf00c849d809cb3cc5eebc43a1924736fd.tar.xz wireguard-linux-17da41bf00c849d809cb3cc5eebc43a1924736fd.zip | |
drm/amdgpu: Remove unnecessary TLB workaround (v2)
This workaround is better handled in user mode in a way that doesn't
require allocating extra memory and breaking userptr BOs.
The TLB bug is a performance bug, not a functional or security bug.
Hence it is safe to remove this kernel part of the workaround to
allow a better workaround using only virtual address alignments in
user mode.
v2: Removed VI_BO_SIZE_ALIGN definition
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c')
0 files changed, 0 insertions, 0 deletions