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| author |   Jiansong Chen <Jiansong.Chen@amd.com> | 2020-02-12 22:32:01 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-07-15 12:46:19 -0400 |
| commit | 026c396b41a4c9412f6f2b6496077949ea99e3ad (patch) | |
| tree | 434c9b2765c2817151d857cdf46d8b5ab1c158d1 /drivers/gpu/drm/amd/amdgpu/navi10_ih.c | |
| parent | drm/amdgpu: add gmc ip block for navy_flounder (diff) | |
| download | wireguard-linux-026c396b41a4c9412f6f2b6496077949ea99e3ad.tar.xz wireguard-linux-026c396b41a4c9412f6f2b6496077949ea99e3ad.zip | |
drm/amdgpu: add ih ip block for navy_flounder
navy_flounder has the same osssys IP verison with
sienna_cichlid, follow its setting.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <Tao.Zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/navi10_ih.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c index 471dc82fd1aa..fdabaf0db3e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c @@ -270,6 +270,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev) if (ih->use_bus_addr) { switch (adev->asic_type) { case CHIP_SIENNA_CICHLID: + case CHIP_NAVY_FLOUNDER: ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_Sienna_Cichlid); ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1); |