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authorDmitry Torokhov <dmitry.torokhov@gmail.com>2020-01-10 14:56:04 -0800
committerDmitry Torokhov <dmitry.torokhov@gmail.com>2020-01-10 14:56:04 -0800
commit1bdd3e05a0a3b4a97ea88bc46fef8fb265c8b94c (patch)
tree2244894a9ea0c941a8f32e5f3d196b4ea0eae24b /drivers/gpu/drm/amd/amdgpu/soc15.h
parentInput: edt-ft5x06 - use pm core to enable/disable the wake irq (diff)
parentLinux 5.5-rc5 (diff)
downloadwireguard-linux-1bdd3e05a0a3b4a97ea88bc46fef8fb265c8b94c.tar.xz
wireguard-linux-1bdd3e05a0a3b4a97ea88bc46fef8fb265c8b94c.zip
Merge tag 'v5.5-rc5' into next
Sync up with mainline to get SPI "delay" API changes.
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/soc15.h')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/soc15.h6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h
index a3dde0c31f57..57af489a5de3 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.h
@@ -28,8 +28,8 @@
#include "nbio_v7_0.h"
#include "nbio_v7_4.h"
-#define SOC15_FLUSH_GPU_TLB_NUM_WREG 4
-#define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT 1
+#define SOC15_FLUSH_GPU_TLB_NUM_WREG 6
+#define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT 3
extern const struct amd_ip_funcs soc15_common_ip_funcs;
@@ -67,6 +67,8 @@ struct soc15_allowed_register_entry {
#define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \
{ ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }
+#define SOC15_REG_FIELD(reg, field) reg##__##field##_MASK, reg##__##field##__SHIFT
+
void soc15_grbm_select(struct amdgpu_device *adev,
u32 me, u32 pipe, u32 queue, u32 vmid);
int soc15_set_ip_blocks(struct amdgpu_device *adev);