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| author |   Monk Liu <Monk.Liu@amd.com> | 2017-03-21 11:50:43 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2017-03-29 23:55:35 -0400 |
| commit | 9ccd52eb248b0d8f0450e1201a8064f5ab1ec07e (patch) | |
| tree | 0c8cfea90d21e04347d7f1b5718168be15e74be4 /drivers/gpu/drm/amd/amdgpu/soc15d.h | |
| parent | drm/amdgpu:implement cond_exec for gfx8 (diff) | |
| download | wireguard-linux-9ccd52eb248b0d8f0450e1201a8064f5ab1ec07e.tar.xz wireguard-linux-9ccd52eb248b0d8f0450e1201a8064f5ab1ec07e.zip | |
drm/amdgpu:enable mcbp for gfx9(v2)
set bit 21 of IB.control filed to actually enable
MCBP for SRIOV
v2:
add flag for preemption enable bit for soc15 and use
this flag instead of hardcode.
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/soc15d.h')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/soc15d.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h b/drivers/gpu/drm/amd/amdgpu/soc15d.h index 7d29329bd642..75403c7c8c9e 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15d.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15d.h @@ -137,6 +137,7 @@ * 1 - Stream * 2 - Bypass */ +#define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) #define PACKET3_COPY_DATA 0x40 #define PACKET3_PFP_SYNC_ME 0x42 #define PACKET3_COND_WRITE 0x45 |