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authorJoshua Aberback <joshua.aberback@amd.com>2020-11-17 11:27:33 -0500
committerAlex Deucher <alexander.deucher@amd.com>2020-12-01 16:03:27 -0500
commit079204508ec0cd32a66c5ca8b9f977383355b181 (patch)
treedd804e750b74960c83311b55e20d5492c9edc7c4 /drivers/gpu/drm/amd/amdgpu
parentdrm/amd/display: Update dram_clock_change_latency for DCN2.1 (diff)
downloadwireguard-linux-079204508ec0cd32a66c5ca8b9f977383355b181.tar.xz
wireguard-linux-079204508ec0cd32a66c5ca8b9f977383355b181.zip
drm/amd/display: Check link_active instead of lane_settings != unknown
[Why] enable_link_dp_mst checks that cur_link_settings != unknown to determine that the link is already enabled, to skip redundant enablement calls for multiple streams on the same link. During dc_reinitialize_hardware, cur_link_settings on previously-active links is not cleared, which blocks MST links from being re-enabled after a reinitialization. [How] - check for link_status->link_active instead, as it's the real intent - clear cur_link_settings when we clear link_active Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
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