diff options
| author |   Mangesh Gadre <Mangesh.Gadre@amd.com> | 2023-06-21 16:55:05 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2023-06-30 13:11:35 -0400 |
| commit | 7f03b1d14d51371fcbb8acba2f8bf037cd8807fa (patch) | |
| tree | 3a318a29857d750663d9ccee097fd2c6b4f93e26 /drivers/gpu/drm/amd/amdgpu | |
| parent | drm/amdgpu: check RAS irq existence for VCN/JPEG (diff) | |
| download | wireguard-linux-7f03b1d14d51371fcbb8acba2f8bf037cd8807fa.tar.xz wireguard-linux-7f03b1d14d51371fcbb8acba2f8bf037cd8807fa.zip | |
drm/amdgpu:Remove sdma halt/unhalt during frontdoor load
sdma halt/unhalt is performed by psp when frontdoor
loading used,so this can be skipped.
v2: Instead of removing halt/unhalt completely,
driver will do it only during backdoor load.
Signed-off-by: Mangesh Gadre <Mangesh.Gadre@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index ea5e12390d18..6be19ffc502b 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -578,6 +578,9 @@ static void sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable, return; } + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) + return; + for_each_inst(i, inst_mask) { f32_cntl = RREG32_SDMA(i, regSDMA_F32_CNTL); f32_cntl = REG_SET_FIELD(f32_cntl, SDMA_F32_CNTL, HALT, enable ? 0 : 1); @@ -904,10 +907,12 @@ static int sdma_v4_4_2_inst_start(struct amdgpu_device *adev, ring->use_doorbell, ring->doorbell_index, adev->doorbell_index.sdma_doorbell_range); - /* unhalt engine */ - temp = RREG32_SDMA(i, regSDMA_F32_CNTL); - temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0); - WREG32_SDMA(i, regSDMA_F32_CNTL, temp); + if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { + /* unhalt engine */ + temp = RREG32_SDMA(i, regSDMA_F32_CNTL); + temp = REG_SET_FIELD(temp, SDMA_F32_CNTL, HALT, 0); + WREG32_SDMA(i, regSDMA_F32_CNTL, temp); + } } } |