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| author |   Michael Strauss <michael.strauss@amd.com> | 2021-08-11 11:38:44 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2021-09-01 16:55:10 -0400 |
| commit | bc204778b4032b336cb3bde85bea852d79e7e389 (patch) | |
| tree | 8aaa30aa2eeb42dfbb5cceae88ffb70f9d58c5e2 /drivers/gpu/drm/amd/amdgpu | |
| parent | drm/amd/display: Support for DMUB HPD interrupt handling (diff) | |
| download | wireguard-linux-bc204778b4032b336cb3bde85bea852d79e7e389.tar.xz wireguard-linux-bc204778b4032b336cb3bde85bea852d79e7e389.zip | |
drm/amd/display: Set min dcfclk if pipe count is 0
[WHY]
Clocks don't get recalculated in 0 stream/0 pipe configs,
blocking S0i3 if dcfclk gets high enough
[HOW]
Create DCN31 copy of DCN30 bandwidth validation func which
doesn't entirely skip validation in 0 pipe scenarios
Override dcfclk to vlevel 0/min value during validation if pipe
count is 0
Reviewed-by: Eric Yang <Eric.Yang2@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Tested-by: Daniel Wheeler <Daniel.Wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
0 files changed, 0 insertions, 0 deletions