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| author |   Reza Amini <Reza.Amini@amd.com> | 2020-07-15 11:33:23 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-08-06 16:40:18 -0400 |
| commit | 471c1dd9546df81d259664ac3e2ab0e99169f755 (patch) | |
| tree | 9c7dfcbbaeedbe03a8cd923733a09745e289d774 /drivers/gpu/drm/amd/display/dc/dc_stream.h | |
| parent | drm/amd/display: Disable idle optimizations before programming DCN (diff) | |
| download | wireguard-linux-471c1dd9546df81d259664ac3e2ab0e99169f755.tar.xz wireguard-linux-471c1dd9546df81d259664ac3e2ab0e99169f755.zip | |
drm/amd/display: Allow asic specific FSFT timing optimization
[Why]
Each asic can optimize best based on its capabilities
[How]
Optimizing timing for a new pixel clock
Signed-off-by: Reza Amini <Reza.Amini@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc_stream.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc_stream.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index e4e85a159462..633442bc7ef2 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -424,8 +424,8 @@ struct dc_stream_status *dc_stream_get_status( struct dc_stream_state *dc_stream); #ifndef TRIM_FSFT -bool dc_optimize_timing( - struct dc_crtc_timing *timing, +bool dc_optimize_timing_for_fsft( + struct dc_stream_state *pStream, unsigned int max_input_rate_in_khz); #endif |