aboutsummaryrefslogtreecommitdiffstatshomepage
path: root/drivers/gpu/drm/amd/display/dc/dc_stream.h
diff options
context:
space:
mode:
authorBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>2020-05-21 12:45:45 -0400
committerAlex Deucher <alexander.deucher@amd.com>2020-07-01 01:59:15 -0400
commitd99f13878d6f9c286b13860d8bf0b4db9ffb189a (patch)
treea64a028d9c3cfc5c480b8125f876e7206e24e5b1 /drivers/gpu/drm/amd/display/dc/dc_stream.h
parentdrm/amd/display: Add DCN3 DMUB (diff)
downloadwireguard-linux-d99f13878d6f9c286b13860d8bf0b4db9ffb189a.tar.xz
wireguard-linux-d99f13878d6f9c286b13860d8bf0b4db9ffb189a.zip
drm/amd/display: Add DCN3 HWSEQ
Add HW sequence programing for DCN3 Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc_stream.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dc_stream.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 49aad691e687..f2ed9bc5a319 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -87,6 +87,13 @@ struct dc_writeback_info {
int dwb_pipe_inst;
struct dc_dwb_params dwb_params;
struct mcif_buf_params mcif_buf_params;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+ struct mcif_warmup_params mcif_warmup_params;
+ /* the plane that is the input to TOP_MUX for MPCC that is the DWB source */
+ struct dc_plane_state *writeback_source_plane;
+ /* source MPCC instance. for use by internally by dc */
+ int mpcc_inst;
+#endif
};
struct dc_writeback_update {
@@ -200,6 +207,10 @@ struct dc_stream_state {
/* writeback */
unsigned int num_wb_info;
struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+ const struct dc_transfer_func *func_shaper;
+ const struct dc_3dlut *lut3d_func;
+#endif
/* Computed state bits */
bool mode_changed : 1;
@@ -251,6 +262,10 @@ struct dc_stream_update {
struct dc_writeback_update *wb_update;
struct dc_dsc_config *dsc_config;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+ struct dc_transfer_func *func_shaper;
+ struct dc_3dlut *lut3d_func;
+#endif
};
bool dc_is_stream_unchanged(