diff options
| author |   Eryk Brol <eryk.brol@amd.com> | 2019-04-23 11:53:52 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-05-31 10:39:30 -0500 |
| commit | e63e2491ad92036e844230b6373ae07923552f6c (patch) | |
| tree | a783cc66c7acfe858213159d7a5069f87b86adf9 /drivers/gpu/drm/amd/display/dc/dc_stream.h | |
| parent | drm/amd/display: Add GSL source select registers (diff) | |
| download | wireguard-linux-e63e2491ad92036e844230b6373ae07923552f6c.tar.xz wireguard-linux-e63e2491ad92036e844230b6373ae07923552f6c.zip | |
drm/amd/display: Ensure DRR triggers in BP
[Why]
In the previous implementation DRR event sometimes came
in during FP2 region which is a keep-out zone. This
would cause the frame not to latch until the next frame
which resulted in heavy flicker. To fix this we need
to make sure that it triggers in the BP.
[How]
1. Remove DRR programming during flip
2. Setup manual trigger for DRR event and trigger it
after surface programming is complete
Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dc_stream.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc_stream.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 189bdab929a5..4da138ded8b7 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -172,7 +172,6 @@ struct dc_stream_update { struct periodic_interrupt_config *periodic_interrupt0; struct periodic_interrupt_config *periodic_interrupt1; - struct dc_crtc_timing_adjust *adjust; struct dc_info_packet *vrr_infopacket; struct dc_info_packet *vsc_infopacket; struct dc_info_packet *vsp_infopacket; |