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| author |   Thomas Lim <Thomas.Lim@amd.com> | 2019-04-29 16:05:42 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-06-11 12:50:50 -0500 |
| commit | 9ed43ef84d9d1e668acdf43c95510fb7b11f8d71 (patch) | |
| tree | d0dc025bc14ff29faf26f5b044e53a14b3943421 /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | |
| parent | drm/amd/display: move vmid determination logic out of dc (diff) | |
| download | wireguard-linux-9ed43ef84d9d1e668acdf43c95510fb7b11f8d71.tar.xz wireguard-linux-9ed43ef84d9d1e668acdf43c95510fb7b11f8d71.zip | |
drm/amd/display: Add Underflow Asserts to dc
[Why]
For debugging underflow issues it can be useful to have asserts when the
underflow initially occurs.
[How]
Read the underflow status registers after actions that have a high risk
of causing underflow and assert that no underflow occurred. If underflow
occurred, clear the bit.
Signed-off-by: Thomas Lim <Thomas.Lim@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h index ef94d6b15843..d3616b1948cc 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h @@ -71,6 +71,8 @@ void dcn10_get_hdr_visual_confirm_color( struct pipe_ctx *pipe_ctx, struct tg_color *color); +bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx); + void update_dchubp_dpp( struct dc *dc, struct pipe_ctx *pipe_ctx, |