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| author |   Yongqiang Sun <yongqiang.sun@amd.com> | 2019-01-25 14:40:14 -0500 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-02-19 15:58:27 -0500 |
| commit | d6001aed266391e05517ff03078c144d4b279d5d (patch) | |
| tree | a1cd7030a53de296dad264489acac40afe5515e0 /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | |
| parent | drm/amd/display: Clear stream->mode_changed after commit (diff) | |
| download | wireguard-linux-d6001aed266391e05517ff03078c144d4b279d5d.tar.xz wireguard-linux-d6001aed266391e05517ff03078c144d4b279d5d.zip | |
drm/amd/display: Refactor for setup periodic interrupt.
[Why]
Current periodic interrupt start point calc in optc
is not clear.
[How]
1. DM convert delta time to lines number and dc will calculate the
start position as per lines number and interrupt type.
2. hwss calculates the start point as per line offset.
3. optc programs vertical interrupts register as per start point
and interrupt source.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h index f8eea10e4c64..6d66084df55f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h @@ -81,4 +81,6 @@ struct pipe_ctx *find_top_pipe_for_stream( struct dc_state *context, const struct dc_stream_state *stream); +int get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx); + #endif /* __DC_HWSS_DCN10_H__ */ |