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| author |   Jun Lei <Jun.Lei@amd.com> | 2018-10-23 12:12:50 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2018-11-19 15:27:36 -0500 |
| commit | eb6b29d62841ec38665840af4c443fbef85bf2ec (patch) | |
| tree | 4977b94f734c2a3fbdc7ef656c770ef9575b092f /drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | |
| parent | drm/amd/display: expose dentist_get_divider_from_did (diff) | |
| download | wireguard-linux-eb6b29d62841ec38665840af4c443fbef85bf2ec.tar.xz wireguard-linux-eb6b29d62841ec38665840af4c443fbef85bf2ec.zip | |
drm/amd/display: make underflow status clear explicit
[why]
HUBP underflow is never cleared, which causes underflow in one
test to fail another test, violating the independence requirements
[how]
Rather than make clearing implicit, we explicitly clear underflow
status in DTN.
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h index 5e5610c9e600..91bb77b468dd 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h @@ -51,6 +51,8 @@ void dcn10_get_hw_state( char *pBuf, unsigned int bufSize, unsigned int mask); +void dcn10_clear_status_bits(struct dc *dc, unsigned int mask); + bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx); bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx); |