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| author |   Alvin Lee <Alvin.Lee2@amd.com> | 2022-08-15 14:58:53 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2022-08-29 17:45:04 -0400 |
| commit | a3c9b4c7a75a66b65b62900e2e9d140e0470cd85 (patch) | |
| tree | a2c9cf1bd2539585d8e6042b7a58cb22c045ee42 /drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | |
| parent | drm/amd/display: Set ODM policy based on number of DSC slices (diff) | |
| download | wireguard-linux-a3c9b4c7a75a66b65b62900e2e9d140e0470cd85.tar.xz wireguard-linux-a3c9b4c7a75a66b65b62900e2e9d140e0470cd85.zip | |
drm/amd/display: Don't choose SubVP display if ActiveMargin > 0
[Description]
There can be SubVP scheduling issues if a SubVP
display is chosen has ActiveDramClockChangeLatency > 0.
Block this case for now, and enable Vactive case
(later) to handle this.
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h index 492aec634b68..da8acf59ccac 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h @@ -312,6 +312,7 @@ struct vba_vars_st { unsigned int ActiveDPPs; unsigned int LBLatencyHidingSourceLinesY; unsigned int LBLatencyHidingSourceLinesC; + double ActiveDRAMClockChangeLatencyMarginPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];// DML doesn't save active margin per state double ActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX]; double CachedActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX]; // Cache in dml_get_voltage_level for debug purposes only double MinActiveDRAMClockChangeMargin; |