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| author |   Matt Roper <matthew.d.roper@intel.com> | 2020-02-20 15:18:43 -0800 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2020-02-26 15:07:42 -0800 |
| commit | 3a1b82a19ff91cfef9b5d9d9faabb0ebcac15df0 (patch) | |
| tree | 94c5295c96144100a882c020e61e72bff4e471a0 /drivers/gpu/drm/i915/display/intel_display_power.h | |
| parent | Merge tag 'gvt-next-2020-02-26' of https://github.com/intel/gvt-linux into drm-intel-next-queued (diff) | |
| download | wireguard-linux-3a1b82a19ff91cfef9b5d9d9faabb0ebcac15df0.tar.xz wireguard-linux-3a1b82a19ff91cfef9b5d9d9faabb0ebcac15df0.zip | |
drm/i915/tgl: Allow DC5/DC6 entry while PG2 is active
On gen12, we no longer need to disable DC5/DC6 when when PG2 is in use
(which translates to cases where we're using VDSC on pipe A).
Bspec: 49193
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200220231843.3127468-1-matthew.d.roper@intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_display_power.h')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_power.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h index 601e000ffd0d..da64a5edae7a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.h +++ b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -100,6 +100,7 @@ enum i915_power_well_id { SKL_DISP_PW_MISC_IO, SKL_DISP_PW_1, SKL_DISP_PW_2, + TGL_DISP_PW_3, SKL_DISP_DC_OFF, }; |