diff options
| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-03-10 02:47:54 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-03-10 17:03:56 +0200 |
| commit | 1fa7bb121401325f91e92a966e84af3075b783ed (patch) | |
| tree | 23317e9f60e6ca34415d2b016efed0e30504218a /drivers/gpu/drm/i915/display/intel_display_types.h | |
| parent | drm/i915: Read DRRS MSA timing delay from VBT (diff) | |
| download | wireguard-linux-1fa7bb121401325f91e92a966e84af3075b783ed.tar.xz wireguard-linux-1fa7bb121401325f91e92a966e84af3075b783ed.zip | |
drm/i915: Program MSA timing delay on ilk/snb/ivb
Grab the DRRS MSA timing delay value from the VBT
and program things accordingly. Only ilk/snb/ivb have
this so presumably on hsw+ we don't need it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220310004802.16310-6-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_display_types.h')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_types.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 5e8d7394a394..86b2fa675124 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1155,6 +1155,7 @@ struct intel_crtc_state { u8 update_planes; u8 framestart_delay; /* 1-4 */ + u8 msa_timing_delay; /* 0-3 */ struct { u32 enable; |