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| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-01-22 17:17:51 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-02-06 15:11:05 +0200 |
| commit | 241d8312131e66f31754659bd49169e1822ac1a8 (patch) | |
| tree | 6df6b604840cade4217bc7032360884a897c12bd /drivers/gpu/drm/i915/display/intel_dp_mst.c | |
| parent | drm/i915/psr: clarify intel_psr_pre_plane_update() conditions (diff) | |
| download | wireguard-linux-241d8312131e66f31754659bd49169e1822ac1a8.tar.xz wireguard-linux-241d8312131e66f31754659bd49169e1822ac1a8.zip | |
drm/i915: Move VT-d alignment into plane->min_alignment()
Currently we don't account for the VT-d alignment w/a in
plane->min_alignment() which means that panning inside a larger
framebuffer can still cause the plane SURF to be misaligned.
Fix the issue by moving the VT-d alignment w/a into
plane->min_alignment() itself (for the affected platforms).
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250122151755.6928-2-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_mst.c')
0 files changed, 0 insertions, 0 deletions