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| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-01-22 17:17:53 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2025-02-06 15:35:44 +0200 |
| commit | 44a34dec43e8f214913e16204525d7253acc1891 (patch) | |
| tree | d553fdde60a33693b209c49651168802d2d399f9 /drivers/gpu/drm/i915/display/intel_dp_mst.c | |
| parent | drm/i915: Use more optimal VTd alignment for planes (diff) | |
| download | wireguard-linux-44a34dec43e8f214913e16204525d7253acc1891.tar.xz wireguard-linux-44a34dec43e8f214913e16204525d7253acc1891.zip | |
drm/i915: Calculate the VT-d guard size in the display code
Currently i915_gem_object_pin_to_display_plane() uses
i915_gem_object_get_tile_row_size() to calculate the tile row
size for the VT-d guard w/a. That's not really proper since
i915_gem_object_get_tile_row_size() only works for fenced BOs,
nor does it take rotation into account.
Remedy the situation by calculating the VT-d guard size in the
display code where we have more information readily available.
Although the default guard size (168 PTEs now) should cover
the more typical fb size use cases anyway, and only very large
Y/Yf-tiled framebuffers might have tile row size that exceeds it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250122151755.6928-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_mst.c')
0 files changed, 0 insertions, 0 deletions