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| author |   Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com> | 2024-12-13 19:59:48 +0100 |
|---|---|---|
| committer |   Andi Shyti <andi.shyti@kernel.org> | 2024-12-20 23:34:43 +0100 |
| commit | 5efc58e409d9e11fc43a029c4186cf6671dd3521 (patch) | |
| tree | c2452a00ee8c5626b7383e4f86e1e2de0cac2a67 /drivers/gpu/drm/i915/display/intel_dp_mst.c | |
| parent | drm/i915/dg1: Fix power gate sequence. (diff) | |
| download | wireguard-linux-5efc58e409d9e11fc43a029c4186cf6671dd3521.tar.xz wireguard-linux-5efc58e409d9e11fc43a029c4186cf6671dd3521.zip | |
drm/i915/selftests: Use preemption timeout on cleanup
Many selftests call igt_flush_test() on cleanup. With default preemption
timeout of compute engines raised to 7.5 seconds, hardcoded flush timeout
of 3 seconds is too short. That results in GPU forcibly wedged and kernel
taineted, then IGT abort triggered. CI BAT runs loose a part of their
expected coverage.
Calculate the flush timeout based on the longest preemption timeout
currently configured for any engine. That way, selftest can still report
detected issues as non-critical, and the GPU gets a chance to recover from
preemptible hangs and prepare for fluent execution of next test cases.
Link: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20241213190122.513709-2-janusz.krzysztofik@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_mst.c')
0 files changed, 0 insertions, 0 deletions