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author | 2025-03-26 15:54:12 -0700 | |
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committer | 2025-03-26 15:54:12 -0700 | |
commit | df02351331671abb26788bc13f6d276e26ae068f (patch) | |
tree | 4e1f8ee707cf6570f39feb47fc5bb151358ebd34 /drivers/gpu/drm/i915/display/intel_dp_mst.c | |
parent | Linux 6.14-rc1 (diff) | |
parent | Merge patch series "riscv: Add runtime constant support" (diff) | |
download | wireguard-linux-df02351331671abb26788bc13f6d276e26ae068f.tar.xz wireguard-linux-df02351331671abb26788bc13f6d276e26ae068f.zip |
Merge tag 'riscv-mw1-6.15-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux into for-next
riscv patches for 6.15-rc1
* A bunch of fixes:
- We were missing a secondary mmu notifier call when flushing the tlb which is required for IOMMU
- Fix ftrace panics by saving the registers as expected by ftrace
- Fix a couple of stimecmp usage related to cpu hotplug
- Fix a bunch of issues in the misaligned probing handling
* Perf improvements:
- Introduce support for runtime constant improving perf of d_hash()
- Add support for huge pfnmaps to improve tlb utilization
- Use Zawrs to improve smp_cond_load8/16() used by the queued spinlocks
* Hwprobe additions:
- Add support for Zicntr and Zihpm
- Add support for Zaamo and Zalrsc
- Add support for bfloat16 extensiosn
- Add support for Zicbom (only enabling clean and flush, not inval for security reasons)
* Misc:
- Add a kernel parameter to bypass the misaligned speed probing since we can't rely on Zicclsm
* tag 'riscv-mw1-6.15-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux: (1585 commits)
riscv: Add runtime constant support
riscv: Move nop definition to insn-def.h
Documentation/kernel-parameters: Add riscv unaligned speed parameters
riscv: Add parameter for skipping access speed tests
riscv: Fix set up of vector cpu hotplug callback
riscv: Fix set up of cpu hotplug callbacks
riscv: Change check_unaligned_access_speed_all_cpus to void
riscv: Fix check_unaligned_access_all_cpus
riscv: Fix riscv_online_cpu_vec
riscv: Annotate unaligned access init functions
KVM: riscv: selftests: Add Zaamo/Zalrsc extensions to get-reg-list test
RISC-V: KVM: Allow Zaamo/Zalrsc extensions for Guest/VM
riscv: hwprobe: export Zaamo and Zalrsc extensions
riscv: add parsing for Zaamo and Zalrsc extensions
dt-bindings: riscv: add Zaamo and Zalrsc ISA extension description
riscv: fgraph: Fix stack layout to match __arch_ftrace_regs argument of ftrace_return_to_handler
riscv: fgraph: Select HAVE_FUNCTION_GRAPH_TRACER depends on HAVE_DYNAMIC_FTRACE_WITH_ARGS
riscv: Fix missing __free_pages() in check_vector_unaligned_access()
riscv: Fix the __riscv_copy_vec_words_unaligned implementation
riscv: mm: Don't use %pK through printk
...
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_mst.c')
-rw-r--r-- | drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 0c44fc7dd86c..86d6185fda50 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -341,6 +341,10 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp, break; } + + /* Allow using zero step to indicate one try */ + if (!step) + break; } if (slots < 0) { @@ -1863,7 +1867,8 @@ intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id) /* create encoders */ mst_stream_encoders_create(dig_port); ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, display->drm, - &intel_dp->aux, 16, 3, conn_base_id); + &intel_dp->aux, 16, + INTEL_NUM_PIPES(display), conn_base_id); if (ret) { intel_dp->mst_mgr.cbs = NULL; return ret; |