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| author |   Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2024-11-13 17:25:31 +0530 |
|---|---|---|
| committer | Ankit Nautiyal <ankit.k.nautiyal@intel.com> | 2024-11-19 14:20:13 +0530 |
| commit | f635e7657e5bb80e1a7a9c3943a3daa71aefd88f (patch) | |
| tree | e014d952f433b0dad8fc81836e63196cd3f3e8fa /drivers/gpu/drm/i915/display/intel_dp_mst.c | |
| parent | drm/i915/psr: Disable psr1 if setup_time > vblank (diff) | |
| download | wireguard-linux-f635e7657e5bb80e1a7a9c3943a3daa71aefd88f.tar.xz wireguard-linux-f635e7657e5bb80e1a7a9c3943a3daa71aefd88f.zip | |
drm/i915/display/xe3lpd: Avoid setting YUV420_MODE in PIPE_MISC
For Xe3_LPD the PIPE_MISC YUV420 Enable (bit 27), already implies enabling
full blend YUV420 mode and YUV420 Mode (bit 26) is removed.
Therefore, avoid setting YUV420 Mode for Xe3_LPD+ while programming
PIPE_MISC for YCbCr420 output format.
Bspec: 69749
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241113115531.3394962-1-ankit.k.nautiyal@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_mst.c')
0 files changed, 0 insertions, 0 deletions