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| author |   Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> | 2023-01-30 15:58:36 +0200 |
|---|---|---|
| committer | Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> | 2023-01-31 10:55:02 +0200 |
| commit | 33d0c67dcbb045cbbbba9d41fa6e4b1f73bf3888 (patch) | |
| tree | 1f15a13a60205a1d19986cc12799e9d9d76e71f4 /drivers/gpu/drm/i915/display/intel_lvds.c | |
| parent | drm/i915/hdmi: Go for scrambling only if platform supports TMDS clock > 340MHz (diff) | |
| download | wireguard-linux-33d0c67dcbb045cbbbba9d41fa6e4b1f73bf3888.tar.xz wireguard-linux-33d0c67dcbb045cbbbba9d41fa6e4b1f73bf3888.zip | |
drm/i915: Implement workaround for CDCLK PLL disable/enable
It was reported that we might get a hung and loss of register access in
some cases when CDCLK PLL is disabled and then enabled, while squashing
is enabled.
As a workaround it was proposed by HW team that SW should disable squashing
when CDCLK PLL is being reenabled.
v2: - Added WA number comment(Rodrigo Vivi)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230130135836.12738-1-stanislav.lisovskiy@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_lvds.c')
0 files changed, 0 insertions, 0 deletions