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authorAndi Shyti <andi@etezian.org>2019-10-24 22:16:41 +0100
committerChris Wilson <chris@chris-wilson.co.uk>2019-10-26 19:28:59 +0100
commit3e7abf8141935ded77abeb622480bf4a14241ece (patch)
treef0a15dd5521fa3b0a98212cc2100e7365055a411 /drivers/gpu/drm/i915/gt/intel_gt_pm.c
parentdrm/i915/tgl: Adjust the location of RING_MI_MODE in the context image (diff)
downloadwireguard-linux-3e7abf8141935ded77abeb622480bf4a14241ece.tar.xz
wireguard-linux-3e7abf8141935ded77abeb622480bf4a14241ece.zip
drm/i915: Extract GT render power state management
i915_irq.c is large. One reason for this is that has a large chunk of the GT render power management stashed away in it. Extract that logic out of i915_irq.c and intel_pm.c and put it under one roof. Based on a patch by Chris Wilson. Signed-off-by: Andi Shyti <andi.shyti@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20191024211642.7688-1-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_gt_pm.c')
-rw-r--r--drivers/gpu/drm/i915/gt/intel_gt_pm.c28
1 files changed, 13 insertions, 15 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index aff4eda47819..32becf15d4e0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -12,8 +12,10 @@
#include "intel_gt.h"
#include "intel_gt_pm.h"
#include "intel_gt_requests.h"
+#include "intel_llc.h"
#include "intel_pm.h"
#include "intel_rc6.h"
+#include "intel_rps.h"
#include "intel_wakeref.h"
static int __gt_unpark(struct intel_wakeref *wf)
@@ -39,12 +41,7 @@ static int __gt_unpark(struct intel_wakeref *wf)
gt->awake = intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ);
GEM_BUG_ON(!gt->awake);
- intel_enable_gt_powersave(i915);
-
- i915_update_gfx_val(i915);
- if (INTEL_GEN(i915) >= 6)
- gen6_rps_busy(i915);
-
+ intel_rps_unpark(&gt->rps);
i915_pmu_gt_unparked(i915);
intel_gt_unpark_requests(gt);
@@ -64,8 +61,7 @@ static int __gt_park(struct intel_wakeref *wf)
i915_vma_parked(gt);
i915_pmu_gt_parked(i915);
- if (INTEL_GEN(i915) >= 6)
- gen6_rps_idle(i915);
+ intel_rps_park(&gt->rps);
/* Everything switched off, flush any residual interrupt just in case */
intel_synchronize_irq(i915);
@@ -97,6 +93,7 @@ void intel_gt_pm_init(struct intel_gt *gt)
* user.
*/
intel_rc6_init(&gt->rc6);
+ intel_rps_init(&gt->rps);
}
static bool reset_engines(struct intel_gt *gt)
@@ -140,12 +137,6 @@ void intel_gt_sanitize(struct intel_gt *gt, bool force)
engine->reset.finish(engine);
}
-void intel_gt_pm_disable(struct intel_gt *gt)
-{
- if (!is_mock_gt(gt))
- intel_sanitize_gt_powersave(gt->i915);
-}
-
void intel_gt_pm_fini(struct intel_gt *gt)
{
intel_rc6_fini(&gt->rc6);
@@ -164,9 +155,13 @@ int intel_gt_resume(struct intel_gt *gt)
* allowing us to fixup the user contexts on their first pin.
*/
intel_gt_pm_get(gt);
+
intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
intel_rc6_sanitize(&gt->rc6);
+ intel_rps_enable(&gt->rps);
+ intel_llc_enable(&gt->llc);
+
for_each_engine(engine, gt, id) {
struct intel_context *ce;
@@ -217,8 +212,11 @@ void intel_gt_suspend(struct intel_gt *gt)
/* We expect to be idle already; but also want to be independent */
wait_for_idle(gt);
- with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+ with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
+ intel_rps_disable(&gt->rps);
intel_rc6_disable(&gt->rc6);
+ intel_llc_disable(&gt->llc);
+ }
}
void intel_gt_runtime_suspend(struct intel_gt *gt)