diff options
author | Chris Wilson <chris@chris-wilson.co.uk> | 2020-03-06 10:08:10 +0800 |
---|---|---|
committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2020-03-06 10:08:10 +0800 |
commit | a61ac1e75105a077ec1efd6923ae3c619f862304 (patch) | |
tree | 31a24e8ae27e3d124e237802c403746dc5108ee2 /drivers/gpu/drm/i915/gvt/execlist.c | |
parent | drm/i915/gvt: Wean gvt off dev_priv->engine[] (diff) | |
download | wireguard-linux-a61ac1e75105a077ec1efd6923ae3c619f862304.tar.xz wireguard-linux-a61ac1e75105a077ec1efd6923ae3c619f862304.zip |
drm/i915/gvt: Wean gvt off using dev_priv
Teach gvt to use intel_gt directly as it currently assumes direct HW
access.
[Zhenyu: rebase, fix compiling]
Cc: Ding Zhuocheng <zhuocheng.ding@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20200304032307.2983-3-zhenyuw@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/execlist.c')
-rw-r--r-- | drivers/gpu/drm/i915/gvt/execlist.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/gvt/execlist.c b/drivers/gpu/drm/i915/gvt/execlist.c index b8aa07c8bcc0..dd25c3024370 100644 --- a/drivers/gpu/drm/i915/gvt/execlist.c +++ b/drivers/gpu/drm/i915/gvt/execlist.c @@ -524,7 +524,7 @@ static void init_vgpu_execlist(struct intel_vgpu *vgpu, static void clean_execlist(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask) { - struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; + struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; struct intel_engine_cs *engine; struct intel_vgpu_submission *s = &vgpu->submission; intel_engine_mask_t tmp; @@ -539,7 +539,7 @@ static void clean_execlist(struct intel_vgpu *vgpu, static void reset_execlist(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask) { - struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; + struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; struct intel_engine_cs *engine; intel_engine_mask_t tmp; |