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| author |   Chris Wilson <chris@chris-wilson.co.uk> | 2019-05-01 12:45:29 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2019-05-02 16:15:26 +0100 |
| commit | 8c334f24e3b4484e059ede14144d16165bb85a20 (patch) | |
| tree | b41d8130a8ba8c8ba63f69a41079d6e64a95c647 /drivers/gpu/drm/i915/intel_runtime_pm.c | |
| parent | drm/i915/icl: Add missing combo PHY lane power setup (diff) | |
| download | wireguard-linux-8c334f24e3b4484e059ede14144d16165bb85a20.tar.xz wireguard-linux-8c334f24e3b4484e059ede14144d16165bb85a20.zip | |
drm/i915: Include fence signaled bit in print_request()
Show the fence flags view of request completion in addition to the
normal hwsp check and whether signaling is enabled.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190501114541.10077-2-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/intel_runtime_pm.c')
0 files changed, 0 insertions, 0 deletions