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| author |   Rajendra Nayak <rnayak@codeaurora.org> | 2020-07-09 16:34:31 +0530 |
|---|---|---|
| committer |   Rob Clark <robdclark@chromium.org> | 2020-07-31 06:46:15 -0700 |
| commit | b0530eb1191307e9038d75e5c83973a396137681 (patch) | |
| tree | bb44252fa740a46f32123b182f8bce732ddaa42b /drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | |
| parent | drm/msm: ratelimit crtc event overflow error (diff) | |
| download | wireguard-linux-b0530eb1191307e9038d75e5c83973a396137681.tar.xz wireguard-linux-b0530eb1191307e9038d75e5c83973a396137681.zip | |
drm/msm/dpu: Use OPP API to set clk/perf state
On some qualcomm platforms DPU needs to express a performance state
requirement on a power domain depending on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index a3b122bfb676..7400cd758a49 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -128,6 +128,10 @@ struct dpu_kms { struct platform_device *pdev; bool rpm_enabled; + + struct opp_table *opp_table; + bool has_opp_table; + struct dss_module_power mp; /* reference count bandwidth requests, so we know when we can |